Le CNFM, DIGILENT et l’école d’ingénieurs ESME-Sudria proposent une formation le JEUDI 2 AVRIL 2020 dans les locaux de l’ESME à PARIS sur le thème:
Integrating Arm Cortex-M Soft CPU IP into FPGA
Description:
This tutorial session will teach attendees the ability to create, program, debug, and develop applications for the Arm Cortex-M1 and M3 soft processors, based in Xilinx FPGAs as part of the Arm DesignStart FPGA program.
To attend this tutorial NO FPGA experience is necessary, the tutorial is majority software focused, with hardware elements using Vivado’s IP Integrator (no VHDL or Verilog coding required).
The tutorial will be split into two sections. The first half of the tutorial will be focused on building foundational knowledge, while the second half will focus on the creation of a simple robot / motor control application. To maximize attendee participation and learning, both parts will be a mixture of presentation of theory and hands-on labs.
Part One – Fundamentals
- Overview of Arm DesignStart FPGA
- Application Use Cases
- Architecture of the Cortex-M1 and Cortex-M3 soft CPUs
- Overview of Development Process
- Lab 1 – Exploring the Architecture in Vivado
- Software development flow / tool chain
- Lab 2 – Saying Hello World
- Debugging the application
Part Two – Creating an Application
In this lab we will use what we have learned in the first session to implement a simple robot / motor control application. This will not only build upon what we have learned in the first session but also introduce new concepts to the attendees such as motor control principles and interfacing the Arm Cortex-M1 and Cortex-M3 soft processors with the outside world.
Matériel: Durant cette formation, nous utiliserons une carte Arty S7-50T prêtée par DIGILENT.
Durée: 4h de formation de 9h à 13h.
Lieu: Ecole ESME (Paris Montparnasse) 40 rue du Docteur Roux – 75015 Paris
Tarif: Gratuit.
Si vous êtes intéressé, merci de confirmer votre présence par retour de mail : gil@lirmm.fr
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